PLL circuits enable a stable oscillation output signal with low phase noise in a certain frequency range by performing feedback control on a tuning control signal input to a voltage-controlled oscillator. In order to reduce phase noise in the oscillation output voltage of the PLL circuit, it is necessary to configure the PLL circuit using a voltage-controlled oscillator with good phase noise characteristics in a wide oscillation frequency range. Most voltage-controlled oscillators with good phase noise characteristics have a wide input range of the tuning control signal. In order to maximize the oscillation frequency range, the PLL circuit is required to output a tuning control signal in a wide voltage range. Below, a PLL circuit which can generate a tuning control signal in a wide voltage range from a low voltage to a high voltage is called a high-voltage PLL circuit.
Conventional high-voltage PLL circuits are generally used as analog PLL circuits, and comprise a charge pump which can output a high-voltage signal. FIG. 5 shows a conventional PLL circuit (first example conventional technology).
The high-voltage PLL circuit comprises a phase detector 1, a level shifter 2, a charge pump 3, a loop filter 4, and a voltage-controlled oscillator (hereinafter, “VCO”) 5. In those units, the phase detector 1 is supplied with a power-supply voltage VCC1 (e.g., 5 V) which is the same value as a power-source voltage supplied to an external controller or the like, and the charge pump 3 is supplied with a power-supply voltage VCC2 (e.g., 16 V) to cause the charge pump 3 to output a high-voltage tuning control signal VC. The VCO 5 is supplied with a power-supply voltage VCC3 (e.g., 8 V). The input voltage range of the tuning control signal VC of the VCO 5 is from 0 V to VCC2. Note that the level shifter 2 is supplied with the power-supply voltage VCC1 and the power-supply voltage VCC2.
The phase detector 1 compares the phase of an output signal OUT from the VCO 5 input through a capacitor 6a with the phase of a reference frequency signal REF supplied from an external reference oscillator 7 through a capacitor 6b, and outputs a pulse signal UP or a pulse signal DN depending on a comparison result. Note that the phase detector 1 includes a divider which performs frequency division on the output signal OUT of the VCO 5 in accordance with a control signal CTRL supplied from an external controller or the like, and the phase detector 1 compares the phase of the output signal OUT having undergone frequency division with the phase of the reference frequency signal REF.
The level shifter 2 performs level shifting on the pulse signal UP or the pulse signal DN output by the phase detector 1 to the input level of the charge pump 3 to output the level shifted signal as a pulse signal UPS, or a pulse signal DNS. Depending on which signal is input: the pulse signal UPS; or the pulse signal DNS, the charge pump 3 generates a current signal with the same fixed magnitude but of a different polarity: positive or negative for the time width of the input pulse signal.
The loop filter 4 is an integration circuit which eliminates high-frequency components from the current signal output by the charge pump 3, and generates a tuning control signal VC for the VCO 5. The VCO 5 generates an output signal OUT having an oscillation frequency which is controlled by a voltage input VC.
In the high-voltage PLL circuit, the phase detector 1 including the divider, the level shifter 2 and the charge pump 3 are integrated on a single chip by utilizing a high-voltage semiconductor process. In those units, the phase detector 1 comprises low-voltage transistors so as to be able to perform high speed operation, and the level shifter 2 and the charge pump 3 comprise high-voltage transistors so as to be able to output a current signal at a high voltage. Note that the capacitors 6a, 6b, the loop filter 4 which utilizes passive elements, and the high-performance VCO 5 which is difficult to be realized as an integrated circuit constitute the high-voltage PLL circuit as external units of the foregoing integrated circuit.
The high-voltage PLL circuit roughly operates as follows. The output signal OUT of the VCO 5 is supplied to a load circuit of a non-illustrated wireless radio front-end or the like and is also fed back to the phase detector 1 through the coupling capacitor 6a. The phase detector 1 causes the divider in the phase detector 1 to perform frequency division on the input signal OUT at a frequency-division ratio set by the control signal CTRL, and compares the phase of the signal having undergone frequency division with the phase of the reference frequency signal REF.
The phase detector 1 outputs a pulse signal UP or a pulse signal DN expressed with two voltage levels, 0 V and VCC1 (i.e., 5 V) depending on advancement or retardation of the phase of the output signal OUT relative to the phase of the reference frequency signal REF. Note that the pulse width of the pulse signal UP or the pulse signal DN is equivalent to the phase difference in time.
The level shifter 2 converts the pulse signal UP and the pulse signal DN to the pulse signal UPS and the pulse signal DNS expressed with two voltage levels, 0 V and VCC1 (i.e., 16 V), and inputs such signals into the charge pump 3. The charge pump 3 outputs a positive or negative constant current signal to the loop filter 4 for a time width of the pulse signal UPS or the pulse signal DNS. For example, when the pulse signal UPS is supplied, a constant current flows out from the charge pump 3 to the loop filter 4. Conversely, when the pulse signal DNS is supplied, the same amount of constant current flows into the charge pump 3 from the loop filter 4. The power-supply voltage VCC2 (16 V) is supplied to the charge pump 3, so that the charge pump 3 can output either positive or negative current signal at an output voltage between 0 V and VCC2.
The loop filter 4 integrates the current signal output by the charge pump 3 to eliminate high-frequency components, generates a tuning control signal VC between 0 V and VCC2, and supplies such a signal to the VCO 5. The tuning control signal VC causes the VCO 5 to control the oscillation frequency of the output signal OUT.
Through the foregoing feedback operation, the output signal OUT having undergone frequency division by the divider in the phase detector 1 is controlled in such a manner as to have the same phase as that of the reference frequency signal REF.
The foregoing first example conventional technology relates to an analog high-voltage PLL circuit, but, also in all digital phase locked loop circuits (hereinafter, “ADPLL circuit”) using a digital/analog converter (hereinafter, “DAC”), a function of generating a tuning control signal in a wide voltage range from a low voltage to a high voltage is employed to configure a high-voltage ADPLL circuits.
One of the characteristics of the ADPLL circuits is that a digital loop filter can be used. The loop filter 4 of the analog PLL circuits generally comprises an external passive element. Accordingly, the loop filter 4 has problems that a large mounting area is necessary, the filter parameters varies within the tolerance of the characteristics of the element, dynamical change of the filter parameters is difficult, and formation of higher-order filter is problematic. In contrast, the digital loop filter has some advantages like, no mounting space is required because it can be implemented inside an integrated circuit, there is no variability in the filter characteristics because filtering is carried out through a logical operation, the filter parameters can be easily changed dynamically by configuring a programmable filter circuit, and formation of a high-order filter is easy. Therefore, the digital loop filter can overcome some of the problems of the analog loop filter.
FIG. 6 shows a configuration of a high-voltage ADPLL circuit as a second example conventional technology. The high-voltage ADPLL circuit comprises a digital phase detector 1D, a digital loop filter 4D, a DAC 8, an operational amplifier (OP) 9, and a VCO 5. In those units, the digital phase detector 1D, the digital loop filter 4D, and the DAC 8 are supplied with a power-supply voltage VCC1 (e.g., 5 V), the operational amplifier 9 is supplied with a power-supply voltage VCC2 (e.g., 16 V) to cause it to output at a high voltage, and the VCO 5 is supplied with a power-supply voltage VCC3 (e.g., 8 V). A tuning control signal VC to the VCO 5 is within an input voltage range from 0 V to VCC2.
The digital phase detector 1D compares the phase of an output signal OUT of the VCO 5 with the phase of a reference frequency signal REF, acquires a phase difference including + or − sign, converts the phase difference into a digital value, and output such a digital value as a phase difference signal. Note that the digital phase detector 1D includes a divider which performs frequency division on the output signal OUT of the VCO 5 according to a control signal CTRL supplied from an external controller or the like, and the digital phase detector 1D compares the phase of a signal having undergone frequency division with the phase of the reference frequency signal REF.
The digital loop filter 4D eliminates high-frequency components from the phase difference signal output by the digital phase detector 1D, and outputs a filtered digital signals. The DAC 8 converts the digital signal output by the digital loop filter 4D into a quantized analog voltage signal from 0 V to VCC1, and outputs such a signal. The operational amplifier 9 amplifies the output voltage signal of 0 V to VCC1 output by the DAC 8 by K times (K=VCC2/VCC1; voltage gain) in order to generate a tuning control signal VC from 0 V to VCC2 which is necessary for the VCO 5. The operational amplifier 9 may be also utilized to apply analog filtering to the output of the DAC 8. The VCO 5 generates an output signal OUT having an oscillation frequency which is controlled by a voltage input VC.
In the high-voltage ADPLL circuit, the digital phase detector 1D, the digital loop filter 4D, DAC 8, and the operational amplifier 9 are integrated on a single chip by utilizing a high voltage semiconductor process. In those units, the digital phase detector 1D, the digital loop filter 4D, and the DAC 8 comprises low-voltage transistors so as to be able to perform both high speed and low power operation. In contrast, the operational amplifier 9 comprises high-voltage transistors so as to be able to output a high-voltage signal. Moreover, the VCO 5 which is difficult to be realized as an integrated circuit constitutes the PLL circuit as an external unit of the foregoing integrated circuit.
According to the high-voltage ADPLL circuit, in comparison with analog high-voltage PLL circuits, there is a difference that internal signals are not analog signal but quantized discrete-time signal. However, like the analog high-voltage PLL circuits, feedback control is performed on the tuning control signal VC in such a way that the phase of the output signal OUT having undergone frequency division by the divider in the digital phase detector 1D matches the phase of the reference frequency signal REF.
Note that Unexamined Japanese Patent Application KOKAI Publication No. 2008-306231 discloses a PLL circuit in which either one of two kinds of pulse signals UP and DN output by a phase detector that can operate with a low power-supply voltage is input into a first differential circuit and a second differential circuit both of which can operate with a high power-supply voltage, and a charge pump outputs an up-current signal or a down-current signal depending on which signal is input: the pulse signal UP, or the pulse signal DN.